Key production process control of high level circuit board
This paper analyzes the main manufacturing difficulties of high-rise circuit board, such as inter layer alignment, inner layer circuit manufacturing, lamination manufacturing, drilling manufacturing and other technical difficulties. In view of the main production difficulties, this paper introduces the key production control points of the key processes, such as the interlayer alignment control, the laminated structure design, the inner layer circuit technology, the laminated technology, the drilling technology and so on, for the reference of the peers.
High level circuit board is generally defined as high-level circuit board with 10-20 layers or more, which is more difficult to process than traditional multi-level circuit board and has high quality and reliability requirements. It is mainly used in communication equipment, high-end server, medical electronics, aviation, industrial control, military and other fields. In recent years, the market demand of high-rise board in application communication, base station, aviation, military and other fields is still strong. With the rapid development of China's telecom equipment market, the market prospect of high-rise board is promising.
At present, the domestic PCB manufacturers that can mass produce high-level circuit boards mainly come from foreign-funded enterprises or a few domestic funded enterprises.
1、 Main production difficulties
Compared with the characteristics of conventional circuit board products, high-rise circuit board has the characteristics of thicker board, more layers, more dense lines and vias, larger unit size, thinner dielectric layer, etc., and the requirements of inner space, inter layer alignment, impedance control and reliability are more stringent.
1.1 difficulty of interlayer alignment
Due to the large number of layers of high-rise boards, the alignment requirements of each layer of PCB at the customer's design end are more and more strict. Generally, the alignment tolerance between layers is controlled within ± 75 μ M. considering the factors such as large unit size design of high-rise boards, environmental temperature and humidity of graphic transfer workshop, as well as the dislocation superposition caused by the inconsistency of rise and fall of different core board layers, and the positioning mode between layers, etc., the alignment control between layers of high-rise boards is more difficult Big.
1.2 difficulties in making inner circuit
High Tg, high-speed, high-frequency, thick copper, thin dielectric layer and other special materials are used in high-rise board, which puts forward high requirements for inner layer circuit manufacturing and graphic size control, such as the integrity of impedance signal transmission, which increases the difficulty of inner layer circuit manufacturing. The line width and line distance are small, the open short circuit is increased, the micro short circuit is increased, and the qualification rate is low; there are many fine circuit signal layers, and the probability of AOI missing inspection of the inner layer is increased; the thickness of the inner core plate is thin, which is easy to wrinkle and lead to poor exposure, and it is easy to roll the plate when etching through the machine; most of the high-rise plates are system plates, with large unit size, and the cost of scrapping the finished products is relatively high.
1.3 difficulties in pressing
When several inner core plates and semi-cured sheets are superposed, defects such as sliding plate, delamination, resin cavity and bubble residue are easy to be produced in the compression production. In the design of laminated structure, it is necessary to fully consider the heat resistance, voltage resistance, filling amount and medium thickness of the material, and set a reasonable high-rise plate compression program. The number of layers is too many to keep the consistency between the rise and fall control and the size coefficient compensation; the thin insulation layer between layers easily leads to the failure of reliability test between layers. Fig. 1 is the defect diagram of bursting plate delamination after thermal stress test.
